CLHS Provides Path to 50 Gbps and Beyond for High-Speed Imaging Applications

By: Bob McCurrach, Director of Standards Development, A3; Mike Miethig, Technical Manager, Teledyne DALSA; and Martin Schwarzbauer, Product Development Manager, Camera Systems, Excelitas PCO

Through an inexpensive IP core, Camera Link HS delivers continually expanding capabilities suited for the future of imaging and machine vision.

Machine vision and imaging applications continue to advance in lockstep with sensor and camera manufacturers as they push the limits of resolution with smaller pixel sizes, increasingly higher pixel counts, and higher frame rates. With larger amounts of image data at increased speeds, interface protocols must also advance.

One of several existing standards is Camera Link High Speed (Camera Link HS or CLHS), a leader in speed, reliability, ease of development, and bandwidth. Upcoming CLHS releases will bring significantly expanded capabilities, with changes that could make it the premier choice for industrial camera interfaces.

Evolving to CLHS

When it was originally released in 2000, Camera Link was a completely volunteer-developed protocol hosted by the Association for Advancing Automation (A3). It offered real-time, high-bandwidth, parallel, two-way communications between a camera and a frame grabber. Beyond real-time high-speed transfer at low latency, Camera Link also provided standardized connectivity with low-cost cables and power over the interface connection (PoCL). 

Camera Link High Speed evolved from Camera Link and was first introduced in 2012. CLHS is built on the low-latency, zero-jitter, real-time strengths of Camera Link while providing scalable bandwidths with extremely reliable data delivery, support for both copper and fiber cabling, and, importantly, intellectual property (IP) cores for ease of component development.

A3 hosts several technical committees that develop and maintain digital interface standards and codes, one of which is CLHS. Currently at version 1.1, CLHS implements its protocol with two physical layer encodings: M Protocol and X Protocol. A3’s VHSIC Hardware Description Language (VHDL) IP cores have been implemented in Altera, Xilinx, and Microsemi field programmable gate arrays (FPGAs). Used in industrial components such as cameras and frame grabbers, the cores are available for $1,000 to help promote the technology.

IP Cores Speed Development

Inexpensive IP cores help camera and frame grabber companies speed CLHS development and implementation while also allowing licensed users to customize cores, since the CLHS IP core is open-source. End users can add features that can be technically reviewed and approved to become a permanent part of the IP core, which allows for continual CLHS interface improvements by the user community. 

The CLHS M Protocol IP core features 8b/10b line encoding for use in lower-cost and lower-power FPGAs. It supports hardware with copper (C2) cabling, with CX4 connections up to 15 meters and 2.1 Gbps in the CLHS cable. Active plug-on fiber cable can be added externally to reach up to 100 meters. Typical bit rates for the M Protocol are up to 5 Gbps per lane.

The CLHS X Protocol IP core is designed for 10 Gbps and higher using 64b/66b line encoding. Other interface protocols, such as CoaXPress (CXP), are moving to this encoding structure. Because of the line encoding technique, CLHS 10 Gbps is equivalent to CXP 12.5 Gbps. Additionally, the X Protocol has forward error correction and single-bit error immunity. 

This protocol natively supports F2 (SFP+) and the soon-to-be-introduced F3 — quad small-form-factor pluggable (QSFP+) and multifiber push-on (MPO) — fiber connections at rates up to 16 Gbps per lane. Copper CX4 (C3) connections are still supported, but the highest data rates and cable lengths (20 kilometers or more in some cases) are realized using fiber cabling. The 64b/66b encoded X Protocol has been in production since 2012 and has a long history of field-tested stability.

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CLHS offers five message types: a low-latency (< 1 µs) 0 ns jitter trigger for real-time imaging at up to 8 MHz with seven separate modes, 16 bidirectional general purpose I/Os with < 1 µs latency, remote DMA video packet and frame grabber data forwarding, high-speed command uplink-enabling streaming correction coefficients, and revision information used in device discovery. A major benefit of CLHS is that it is a real-time, point-to-point interface. In the context of the CLHS triggers and GPIO, the low latency provides immediate responses, eliminating the need for tracking and scheduling, as might be the case with other interfaces. 

The CLHS X Protocol can connect to a 10GBASE-KR Ethernet physical layer (PHY) for FPGAs without built-in 10 Gbps transceivers or can use the provided physical coding sublayer (PCS) module to implement the code within 10 Gbps–capable FPGAs that don’t offer 10GBASE-KR capability. Because of the unique way the CLHS X Protocol is implemented, Camera Link HS is already in the final stages of moving the specification to 25 Gbps.

From 25 Gbps to 50 Gbps and Beyond 

CLHS IP architecture allows the standard to move to 25 Gbps on an FPGA using 25 Gbps transceivers over fiber with SFP28, QSFP28, or MPO connectors. The upcoming specification revision will validate CLHS as having up to 100 Gbps (4 × 25 Gbps) available bandwidth using a single MPO connector. But the CLHS X Protocol IP core will not change — nor will any CLHS infrastructure — making the move to 25 Gbps inexpensive and straightforward for companies and end users.

In addition, CLHS offers a flexible and robust mechanism for changing the speed of the interface, as MPO to LC, breakout cables, or SFP28 allows backward compatibility to existing CLHS 10 Gbps frame grabbers or newly developed 25 Gbps frame grabbers to support existing 10G cameras. 

With FPGA and PHY technology ready to support 50 Gbps and higher rates, CLHS can deliver powerful real-time camera interface capabilities at even higher imaging rates, which will help in challenging imaging applications requiring high speeds and high data rates. The CLHS working group has taken the existing X Protocol IP core and built a simple bridge from the 64 bit output of the X Protocol IP core PCS to the 128 bit input of 50 Gbps FPGAs with built-in SerDes blocks.

To achieve 50 Gbps speeds, the CLHS standard will introduce a virtual channel using a master and slave channel (or lane) all in one fiber. With this minor change in the specification, component companies can easily migrate to the higher-speed interfacing with minimal impact on hardware and software architecture.

CLHS Moving Forward

With its IP cores, open-source VHDL, and advanced line encoding and error correction, CLHS is well positioned for the future of imaging. CLHS support for fiber cabling will also help with future-proofing. Fiber cable is robust and less likely to bend, wrap, or pinch than copper wire alternatives. It is also easier to use, field installable, and modifiable. Additionally, fiber can carry more than twice the bandwidth of copper at up to many kilometers and is less expensive.

Moving forward, CLHS will continue to improve, but its use of 64b/66b encoding in 2012 still provides manufacturers and end users with a long design cycle, from 10 Gbps all the way up to 50 Gbps. The unique features and capabilities of CLHS solidify the standard as a definitive choice in high-speed imaging applications both now and into the future.