Camera Link HS Version 1.2 Updates
Outside of attending a major global machine vision show like Automate or taking part in an International Vision Standards Meeting, keeping up with machine vision standards updates can be difficult. Version 1.2 of Camera Link HS (CLHS), for example, was introduced in late 2022 at The Vision Show in Boston.
At that time, it was announced that a major speed upgrade would be made possible through use of the X protocol. CLHS implements its protocol with two physical layer encodings: M protocol and X protocol. As part of the update, it was announced that CLHS would be able to move to speeds of 25 Gbps on an FPGA using 25 Gbps transceivers over fiber with SFP28, QSFP28, or MPO connectors. This update was ultimately made possible through A3’s CLHS IP core, which costs only $1,000 and speeds CLHS product development.
>>>Related: View more information on CLHS here.
Now, the speed increase has been made official for the CLHS X protocol. Mike Miethig, R&D Camera Development Manager at Teledyne DALSA and Chair of the Camera Link HS committee, wrote in his “What’s New in CLHS Version 1.2,” Vision Systems Design article that with this update, CLHS is the only standard that offers 0 jitter bidirectional triggers and very low latency (<0.5 µs) bidirectional general-purpose input/output (GPIO).
In addition, CLHS 25 Gbps is also backward compatible to 10 Gbps CLHS, meaning that the optical engines that work at 25G also work at 10G. When a camera and frame grabber power on, the system begins at 10G and establishes a command channel. The frame grabber then reads the mandatory register list and recognizes that the camera supports 25G and follows the defined procedure to command the camera to 25G and drops the link. The camera and frame grabber then reestablish the link at 25G, and if the link fails to establish after a time, the devices revert to 10G and reestablish the link in a fail-safe manner.
Miethig discusses the additional benefits of backward compatibility while also taking an in-depth look at additional updates and topics, including the CLHS IP core and its features, CLHS product development using the IP core, FPGA implementation, and future CLHS plans.
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